NXP Semiconductors /MIMXRT1021 /PWM1 /SM0TCTRL

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Interpret as SM0TCTRL

TRGFRQ=EVERYPWM, PWBOT1=PWM_OUT_TRIG1_SIGNAL, PWAOT0=PWM_OUT_TRIG0_SIGNAL

Description

Output Trigger Control Register

Fields

OUT_TRIG_EN	Output Trigger Enables 1 (VAL0): PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
TRGFRQ	Trigger frequency 0 (EVERYPWM): Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 1 (FINALPWM): Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
PWBOT1	Mux Output Trigger 1 Source Select 0 (PWM_OUT_TRIG1_SIGNAL): Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. 1 (PWMB_OUTPUT): Route the PWMB output to the PWM_MUX_TRIG1 port.
PWAOT0	Mux Output Trigger 0 Source Select 0 (PWM_OUT_TRIG0_SIGNAL): Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. 1 (PWMA_OUTPUT): Route the PWMA output to the PWM_MUX_TRIG0 port.

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